1. Field of the Invention
This invention relates generally to computer memory and, more particularly, to system and method for accessing data in a multicycle operations cache.
2. Description of the Related Art
As on-chip memory size continues to increase with technology scaling, the increase in the size of a cache memory also increases access time of data in the cache memory because longer data lines are used. Thus, data that typically takes only one clock cycle to access may take up to two clock cycles to access in a large cache memory. Accordingly, in a large cache memory, data access may take multiple clock cycles. The problem with accessing data in a multicycle operations cache is that a traditional memory controller may issue an access request at every single clock cycle. If a request is made while the cache memory is still servicing a prior request, the data accessed becomes corrupted as the accessing of the data is interrupted by the subsequent request. The memory controller can be designed to issue the data request based on an array latency, but this approach creates multicycle paths in the memory controller which makes timing and functional variations difficult and error prone.
Furthermore, the power consumption of large cache memories, such as level-1 (L1) cache, level-2 (L2) cache, level-3 (L3) cache, etc., during an idle state becomes an important factor of total power consumption. For example, excessive power consumptions by cache memories become particularly troublesome during wafer testing because a full power supply is not available.
As a result, there is a need to provide system and method to access data in a multicycle operations cache without access data corruption, and to minimize power consumption of cache memories.